Service
Data acquisition (DAQ) system design
We design data acquisition systems from sensor to bits: the analog front-end, the acquisition architecture on FPGA or MCU, the deterministic firmware that samples it, and the bench validation that proves the numbers. For test and measurement, industrial, and scientific products where the measurement itself is the product. Every engagement is run by one team across the whole chain, so the analog, the logic, and the firmware are engineered as one system.
Scope
What a DAQ engagement covers
- Analog front-end and signal conditioning, designed end to end (analog circuit design services)
- Acquisition architecture on FPGAs (RTL written in-house, Verilog/VHDL) or MCUs (STM32, ESP32, ARM Cortex-M, 8/16/32-bit PIC)
- Clocking and trigger architectures for exact, repeatable sample rates
- High-throughput data paths: LPDDR4 waveform buffering, USB 3.x, Gigabit Ethernet, PCIe Gen4
- Deterministic bare-metal firmware: DMA- and interrupt-driven sampling with minimal jitter
- Bench characterization (noise floor, sample-rate accuracy, linearity) and production handoff
Proof
Delivered systems
Every claim on this page is backed by a system we shipped, each delivered from analog front-end to RTL and firmware:
| 100 MSPS · 8-channel · 12-bit | DAQ system on Zynq-7000 → |
|---|---|
| 1 GSPS · dual-channel · 8-bit | Acquisition system on Zynq-7000 → |
| 16-bit · 15 MSPS · 20 µV | Wide-bandwidth precision system → |
Fact sheet
Capability bounds
These are the bounds of systems already delivered, not aspirations. If your requirements sit inside them, an engagement can be scoped quickly; if they sit outside, the scoping call will say so honestly.
| ADC resolution | 8 to 24-bit (front-ends for 16 to 24-bit delta-sigma and SAR) |
|---|---|
| Sampling rates | Up to 1 GSPS delivered |
| Platforms | Xilinx Zynq-7000; STM32, ESP32, ARM Cortex-M, PIC MCUs |
| Firmware | Deterministic bare-metal C |
| Smallest resolved signal | 20 µV |
How we work
How an engagement runs
Defined projects run on fixed-price milestones agreed after a short scoping call, moving through design with review gates, bench validation, and production handoff. Open-ended R&D work runs hourly, with regular updates and a clear summary of what was done and what is next. Not sure which model fits? Send what you have and you’ll get a recommendation, not a sales call.
FAQ
Common questions
Should my DAQ system use an FPGA or an MCU?
Both are viable and we design with both. MCUs (STM32, ESP32, ARM Cortex-M, PIC) suit many precision channels at moderate rates; FPGAs (such as Zynq-7000) suit high-throughput, multi-channel, and exactly timed acquisition. The choice follows your sample rates, channel count, and data volumes.
Do you write the FPGA RTL yourselves?
Yes. All RTL (Verilog/VHDL) is written in-house, together with the clocking and trigger architectures that make sample rates exact and repeatable.
What does an end-to-end engagement include?
Analog front-end, mixed-signal PCB, FPGA logic or MCU firmware, and bench validation: noise floor, sample-rate accuracy, and linearity measured in our own lab before delivery.
What do you need to quote a system?
Sample rate, resolution, channel count, and host interface are the core inputs. A rough idea is enough to start; you will get an approach and a timeline.
How is a DAQ project priced?
Defined systems are typically delivered for fixed-price milestones agreed after a short scoping call. Open-ended R&D work runs hourly with regular updates.
Contact
Building a system that measures?
Send your spec or a rough idea and you’ll get an approach and a timeline, not a generic pitch.